The present invention relates generally to the field of FINFETs (fin-including field-effect transistors), and more particularly to fabrication of FINFETs that are located over an oxide layer.
FINFET (or “FINFET”) means any fin-based, multigate transistor architecture regardless of number of gates. Typically, a FINFET includes a nonplanar, multiple-gate transistor built on an SOI (silicon-on-insulator) substrate, where a conducting channel is wrapped by a thin silicon “fin.” The wrap-around gate structure provides a better electrical control over the channel and thus helps in reducing the leakage current and overcoming other short-channel effects. The insulator layer of the substrate is typically a buried oxide layer (or BOX), made of a material such as silicon dioxide (SiO2).
In conventional methods for fabricating FINFETs, growing an epitaxial source-drain region from the silicon substrate allows good quality, highly-strained regions to form surrounding the channel region of the FINFET. For bulk FINFET devices, this allows for higher performance due to increased mobility from the strain. Unfortunately, bulk FINFETs suffer from fin width variability due to the STI (shallow trench isolation) recess which can add to device variability. SOI (silicon on insulator) FINFETs, by comparison, have the advantage that the device width is defined by the silicon above the buried oxide (BOX), and not by the STI recess, leading to less device variability.